1. Technical Field
The present invention relates in general to a method and system for data processing and, in particular, to a method and system for handling Peripheral Component Interconnect (PCI) local bus accesses within a computer system. Still more particularly, the present invention relates to a method and system for determining the optimal burst length along a PCI bus utilizing a cache-line size of a PCI Host Bridge and a target adapter""s latency timer value within a computer system.
2. Description of the Related Art
A computer system typically includes several types of buses, such as a system bus, local buses, and peripheral buses. Various electronic circuit devices and components are connected through the use of adapters with each other via these buses such that intercommunication may be possible among all of these devices and components. In general, a central processing unit (CPU) is attached to a system bus, over which the CPU communicates directly with a system memory that is also attached to the system bus. In addition, a local bus may be used for connecting certain highly integrated peripheral components rather than the slower standard expansion bus. One such local bus is known as the Peripheral Component Interconnect (PCI) bus.
Under the PCI local bus standard, peripheral components can directly connect to a PCI local bus without the need for glue logic, the xe2x80x9cprofusion of chips needed to match the signals between different integrated circuits.xe2x80x9d Thus, PCI provides a bus standard on which high-performance peripheral devices, such as graphics devices and hard disk drives, can be coupled to the CPU through the use of PCI adapters, thereby permitting these high-performance peripheral devices to avoid the general access latency and bandwidth constraints. These peripheral devices typically include input/output (I/O) devices such as a keyboard, floppy drives, and printers. Some PCI adapters allow software to control the amount of data the adapter will burst across the PCI bus in a single bus ownership. Therefore, the burst length may make a significant (positive or negative) impact on performance.
Furthermore, if the burst length is too low, required throughput rates for some PCI devices may not be achieved. If the burst length is too high, other PCI devices may experience underruns. Also, an excessive burst length may lead to inefficient subsequent accesses to memory, if the latency timer expires in mid-burst and the PCI device needs to realign to a cache boundary before resuming full bursts. The problem of choosing a burst value is complicated by the fact that the optimal value is dependent on the particular PCI Host Bridge being used, PCI bus speed, and the requirements of other PCI devices on the same bus.
Therefore, it is desirable in a PCI-based system requiring multiple PCI host bridges supporting multiple PCI buses, that optimal burst lengths be chosen to help take advantage of data pre-fetching by the PCI Host Bridge, thereby increasing throughput and memory bus efficiency. The subject invention herein solves all these problems in a new and unique manner that has not been part of the art previously.
In view of the foregoing, it is therefore an object of the present invention to provide an improved method and system for data processing.
It is another object of the present invention to provide an improved method and system for choosing the optimal PCI adapter burst length
In accordance with the method and system of the present invention, the optimal burst length is automatically determined by the adapter configuration feature of AIX software using a cache-line size of a PCI bridge and the latency timer value of the target PCI adapter as inputs. The method also provides for a user to be able to override the software-calculated setting.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.